1. Technical Field
The present invention relates in general to a method and system for data processing and, in particular, to a method and system for handling multiple Peripheral Component Interconnect (PCI) local bus accesses within a computer system. Still more particularly, the present invention relates to a method and system for handling PCI peer-to-peer access across multiple PCI local buses across a PCI host bridge supporting multiple PCI Buses within a computer system.
2. Description of the Related Art
A computer system typically includes several types of buses, such as a system bus, local buses, and peripheral buses. Various electronic circuit devices and components are connected with each other via these buses such that intercommunication may be possible among all of these devices and components.
In general, a central processing unit (CPU) is attached to a system bus, over which the CPU communicates directly with a system memory that is also attached to the system bus. In addition, a local bus may be used for connecting certain highly integrated peripheral components rather than the slower standard expansion bus. One such local bus is known as the Peripheral Component Interconnect (PCI) bus. Under the PCI local bus standard, peripheral components can directly connect to a PCI local bus without the need for glue logic, the "profusion of chips needed to match the signals between different integrated circuits." Thus, PCI provides a bus standard on which high-performance peripheral devices, such as graphics devices and hard disk drives, can be coupled to the CPU, thereby permitting these high-performance peripheral devices to avoid the general access latency and the bandwidth constraints that are associated with an expansion bus. An expansion bus such as an Industry Standard Architecture (ISA) bus, is for connecting various peripheral devices to the computer system. These peripheral devices typically include input/output (I/O) devices such as a keyboard, floppy drives, and printers.
Additionally, under the PCI local bus standard for 33 MHz operation, only four peripheral component connector slots may be attached to the PCI bus due to loading constraints on the bus. In order to overcome this technical constraint, designers may add a second or more PCI local buses that give the end user of a computer system the advantage of adding on four more slots per bus. However, a PCI host bridge is required for transferring information from the PCI bus to the system bus. Therefore, with the addition of more than one PCI local buses, designers have had to add on multiple PCI host bridges and/or PCI-to-PCI bridges for supporting the multiple PCI buses and a method for handling PCI peer-to-peer access across the multiple PCI host bridges thereby increasing the cost and complexity of the system.
Therefore, it is desirable in a PCI-based system requiring multiple PCI host bridges and/or PCI-to-PCI bridges supporting multiple PCI buses, that a single PCI host bridge support multiple PCI buses thus minimizing the number of required bridges. Furthermore, it is desirable to have a single PCI host bridge operating at 33 MHz that has the capability of supporting more than four peripheral component slots having PCI devices connected thereto. Additionally, it is desirable to support PCI peer-to-peer access across a PCI bus operating at 33 MHz within a data-processing system. The subject invention herein solves all these problems in a new and unique manner which has not been part of the art previously.